Binary bits stored in a standard DRAM are represented by the voltage values of charge stored in capacitors. The capacitors are typically formed of insulated gate field effect transistors (FETs). Charge is written to a capacitor by applying a voltage from a bit line through the source-drain circuit of a pass field effect transistor, which is enabled by applying an address signal from a word line to the gate of the pass transistor.
To speed up reading from or writing charge to the capacitor, the bit line and the capacitor are typically first precharged to a value of half of a power rail voltage, e.g. Vdd/2. When the actual value of a 0 or 1 bit is to be stored, e.g. nominally to Vss or Vdd, the time for the full charge to be passed to or removed from the capacitor to achieve the nominal Vss or Vdd voltage is thereby reduced since the capacitor will already have about half the voltage required to achieve the ultimate bit value.
A structure which illustrates the above in a standard DRAM is shown in FIG. 1A, and a graph illustrating voltage with at two different supply voltages is shown in FIG. 1B.
A pass FET 1 is shown having its source-drain circuit connected between a plate of charge storage capacitor 3 and a bit line BL. The gate of FET 1 is connected to a word line WL. The bit line is connected through a precharge enable FET 5 to a source of bit line precharge voltage Vblp=Vdd/2. A precharge enable logic signal is applied to the gate of FET 5, to cause the bit line to be precharged to Vdd/2.
A source of cell plate precharge voltage Vcp=Vdd/2 is applied to the other plate of the capacitor 3. Operation of the above-described circuit to write and read charge (bits) on capacitor 3 is well known to those skilled in the art and need not be described further herein.
With reference to FIG. 1B, the precharge voltages are shown as the voltage represented by the middle horizontal line, values Vcp and Vblp which have the voltage value Vdd/2. The voltage values Vdd and Vss relative to Vdd/2 are also shown. The value of a bit "0" is the lower dashed line, approximately Vss (ground) separated from the value Vdd/2 by the value "x". The value of a bit "1" is the higher dashed line, which is approximately Vdd, separated from the value Vdd/2 by the value "x". The two values "x" are substantially the same.
When using conventional Vdd/2 precharge for the bit lines, a proportion (approximately half) of any change in Vdd between write and read operations detracts from the signal margin, as can be shown in what is generally known as a "bump test", wherein the supply voltage is changed.
If the supply voltage changes (e.g. is "bumped") between the time a cell is written and the time a cell is read, both of the values "x" remain the same as before, since both Vcp and Vblp remain equal to Vdd/2, as shown at the right hand portion of FIG. 1B.
However, in an application specific integrated circuit (ASIC) DRAM cell such as one described in U.S. patent application Ser. No. 08/355,956 filed Dec. 14, 1994, invented by K. Skjaveland and P. Gillingham, the cell capacitor plate must be held at a voltage other than Vdd/2, such as at Vdd or Vpp (where Vpp=Vdd+Vtn), in order to turn on the channel of the p-channel FET of which the capacitor is formed.
Problems with the ASIC form of DRAM cell result from the p-doped substrate having Vss connected to it, rather than a back bias voltage as is used in standard memory processes. Since there is no back bias voltage on the memory cell access FET, subthreshold leakage from the capacitor is undesirably high.
The ASIC process does not allow the use of the pluralized standard DRAM cell techniques such as trench cells, etc. Further, as noted above, no back bias (VBB) negative voltage is permitted in ASIC process.
In the aforementioned patent application the source/drain of the capacitor FET serves as a capacitor cell plate and must be biased to either a positive supply rail (in the case of PMOS cell implementation) or to ground (in the case of an NMOS cell implementation.)
FIG. 2A illustrates the prior art structure, which is similar to FIG. 1A except that the capacitor is formed of an FET and the precharge voltage Vcp =Vpp=(Vdd+Vtn). In this case the voltages are as illustrated in FIG. 2B. Alternately, the cell plate may be connected directly to Vdd.
Prior to the voltage "bump", the difference in voltage between Vss and Vblp is "x", (Vdd/2 ), and the difference in voltage between Vdd and Vblp is also the same value "x", (Vdd/2). Both voltage differences "x" are substantially the same.
However, after the voltage "bump", the value of a "0" is the difference between the raised voltage from Vss and Vblp, which is shown as "z", while the value of a "1" is the difference between Vblp and the raised value of approximately Vdd. Clearly the values of "y" and "z" after the "bump" are not the same as the signals "x", and the value "z" is smaller than the value "y". Thus the "0" voltage margin has been lost. If the bump was negative, the "1" voltage margin would be lost. This effectively introduces noise, making the values of "0" and "1" less reliable than in the case of the circuit of FIG. 1A.